The subject matter of this disclosure relates generally to ultra-low power analog-to-digital conversion for portable applications, and more particularly, to ultra-low power analog to digital converters (ADCs) that enable maintaining power dissipation in a digital ultrasound probe and prevent temperature rise from exceeding 43° C.
Ultra-low power ADCs, that consume less than 5 mW while performing 12 bit conversions at 50 MSPS, are required for some applications such as a digital ultrasound probe. This is necessary to maintain the overall power dissipation in the probe and prevent temperature rise from exceeding 43° C., which is a regulatory cutoff limit. Most commercial ADCs operating at this speed and resolution typically consume 20 mW or higher, which is too high to integrate into a digital probe. An integrated solution wherein the analog to digital converter (ADC) directly drives the digital beam-former built in a single ASIC offers some power saving benefits in the interconnect. However, the core ADC will still consume a significant amount of power if implemented with standard analog to digital conversion techniques.
Conventional techniques include ramp and sigma-delta converters for low speed, high resolution converters, and pipelined converters for higher speed designs. Single stage Successive Approximation Register (SAR) converters are popular in the moderate range of ˜10 bits. The advent of modern sub-90 nm CMOS processing has pushed the speed limits of such converters in to the tens of MHz range.
The advent of deep-sub micron CMOS processes enables low power digital calibration. However, the power required by analog components in the data converter does not scale. Hence, the advantage shifts to “analog light” converter design. Recent literature shows that pipelining a SAR converter to improve resolution and push to higher speed is gaining importance. Some of these approaches have limitations in the design implementation.
Time-interleaving multiple ADCs, for example, is an option if power consumption and larger area can be afforded. Sharing op-amps to reduce power is also a popular technique, but is limited to lower speeds. Another technique includes the use of dynamic comparators, but is limited in resolution. A class of ADCs known as predictive ADCs that take advantage of signal properties has also been investigated. While knowing the signal properties can help take advantage of this in an algorithmic converter and achieve significant power savings, the issue of prediction failure is not well addressed. It typically means building two ADCs, one full power that is active for a part of the time and a predictive converter operating most of the time. Other approaches include minimizing the number of system channels and reducing resolution or speed, all of which adversely affect image quality.
In view of the forgoing, it would be advantageous to provide an ultra-low power ADC architecture for portable applications such as a digital ultrasound probe. The ultra-low power ADC architecture should enable the digital ultrasound probe to maintain a desired power dissipation and prevent a temperature rise from exceeding 43° C.